In three-dimensional integrated circuit (3DIC) formation process, device dies may be bonded to a wafer. Typically, after the bonding of the dies onto the wafer, a molding compound is applied to encapsulate the device dies and the wafer. Solder bumps are formed on the wafer to electrically couple to the devices in the wafer. The electrical connection to the devices in the device dies and the devices in the wafer includes through-silicon vias (TSVs).
After the molding compound is applied, a die saw is performed to saw apart the wafer and the device dies into dies, wherein each of the dies may include one of the device dies and one of the chips in the wafer. The die saw is typically performed using a blade, which cuts through the scribe lines in the wafer. Since the wafer may include low-k dielectric materials, the mechanical stress applied by the blade may cause cracks. The cracks in the low-k dielectric materials may propagate to the chips in the wafer, resulting in yield loss. Accordingly, to reduce the yield loss, the process window for the blade dicing is limited.